A Petri Net Tool for Software Performance Estimation Based on Upper Throughput Bounds

Functional and non-functional properties analysis (i.e., dependability, security, or performance) ensures that requirements are fulfilled during the design phase of software systems. However, the Unified Modelling Language (UML), standard de facto in industry for software systems modelling, is unsuitable for any kind of analysis but can be tailored for specific analysis purposes through profiling. For instance, the MARTE profile enables to annotate performance data within UML models that can be later transformed to formal models (e.g., Petri nets or Timed Automatas) for performance evaluation. A performance (or throughput) estimation in such models normally relies on a whole exploration of the state space, which becomes unfeasible for large systems. To overcome this issue upper throughput bounds are computed, which provide an approximation to the real system throughput with a good complexity-accuracy trade-off. This paper introduces a tool, named PeabraiN, that estimates the performance of software systems via their UML models. To do so, UML models are transformed to Petri nets where performance is estimated based on upper throughput bounds computation. PeabraiN also allows to compute other features on Petri nets, such as the computation of upper and lower marking place bounds, and to simulate using an approximate (continuous) method. We show the applicability of PeabraiN by evaluating the performance of a building closed circuit TV system

Modelling and PID Control of a Rotary Dryer

This paper describes the modelling and the PID control of a drying process. The plant uses a co-current rotary dryer to evaporate moisture of a waste product generated by olive-oil mills, called alpeorujo or two phase cake. The paper shows the development of a model based upon first principles combined with experimental results. A control strategy has been tested under simulation based on PID controllers for the main loops in this process

Robust symmetric multiplication for programmable analog VLSI array processing

This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several blocks: a linearized transconductor, binary weighted current mirrors and a differential to single-ended current adder. This paper shows the advantages introduced using a linearized OTA-based multiplier. The circuit presented renders higher linearity and symmetry in the output current than a previously reported single-transistor multiplier. Its inclusion in an array processor based on CNN allows for a more accurate implementation of the processing model and a more robust weight distribution scheme than those found in previous designs.Office of Naval Research (USA) N-00014- 02-1-0884Ministerio de Ciencia y Tecnología TIC2003-09817-C02-0

A Focal-Plane Image Processor for Low Power Adaptive Capture and Analysis of the Visual Stimulus

Portable applications of artificial vision are limited by the fact that conventional processing schemes fail to meet the specifications under a tight power budget. A bio-inspired approach, based in the goal-directed organization of sensory organs found in nature, has been employed to implement a focal-plane image processor for low power vision applications. The prototype contains a multi-layered CNN structure concurrent with 32times32 photosensors with locally programmable integration time for adaptive image capture with on-chip local and global adaptation mechanisms. A more robust and linear multiplier block has been employed to reduce irregular analog wave propagation ought to asymmetric synapses. The predicted computing power per power consumption, 142MOPS/mW, is orders of magnitude above what rendered by conventional architectures

Mercado laboral de las personas discapacitadas en España

En este trabajo, partiendo de un análisis inicial basado en el estudio de las políticas públicas dirigidas a las personas discapacitadas y de los problemas en la definición de la discapacidad, se analizan las características sociodemográficas de las personas discapacitadas en edad de trabajan y aquellas que están trabajando. A partir de la información disponible en el Panel de Hogares de la Unión Europea para el año 1998, los resultados obtenidos permiten afirmar que uno de los principales obstáculos para la integración laboral de las personas discapacitadas se sitúa en la primera fase del proceso de inserción, es decir, en pasar de la inactividad a la actividad. Estos resultados tienen implicaciones en las futuras políticas públicas dirigidas a favorecer la integración laboral y social de este colectivo.________________________________In this piece of work, beginning with a preliminary analysis of the public policies for disabled persons and the problems associated to the concept of disability, we analyse the sociodemographics characteristics of working age and employed disabled persons in Spain. Using the data from the European Household Panel for 1998, our results show that the main barrier for the labour integration of the disabled person is found in the first phase of the process, this is to say, from the inactivity to labour activity. These results have implication for the future public policies lead to this specific group

On the Performance Estimation and Resource Optimisation in Process Petri Nets

Many artificial systems can be modeled as discrete dynamic systems in which resources are shared among different tasks. The performance of such systems, which is usually a system requirement, heavily relies on the number and distribution of such resources. The goal of this paper is twofold: first, to design a technique to estimate the steady-state performance of a given system with shared resources, and second, to propose a heuristic strategy to distribute shared resources so that the system performance is enhanced as much as possible. The systems under consideration are assumed to be large systems, such as service-oriented architecture (SOA) systems, and modeled by a particular class of Petri nets (PNs) called process PNs. In order to avoid the state explosion problem inherent to discrete models, the proposed techniques make intensive use of linear programming (LP) problems

MOSTO: A toolkit to facilitate security auditing of ICS devices using Modbus/TCP

The integration of the Internet into industrial plants has connected Industrial Control Systems (ICS) worldwide, resulting in an increase in the number of attack surfaces and the exposure of software and devices not originally intended for networking. In addition, the heterogeneity and technical obsolescence of ICS architectures, legacy hardware, and outdated software pose significant challenges. Since these systems control essential infrastructure such as power grids, water treatment plants, and transportation networks, security is of the utmost importance. Unfortunately, current methods for evaluating the security of ICS are often ad-hoc and difficult to formalize into a systematic evaluation methodology with predictable results. In this paper, we propose a practical method supported by a concrete toolkit for performing penetration testing in an industrial setting. The primary focus is on the Modbus/TCP protocol as the field control protocol. Our approach relies on a toolkit, named MOSTO, which is licensed under GNU GPL and enables auditors to assess the security of existing industrial control settings without interfering with ICS workflows. Furthermore, we present a model-driven framework that combines formal methods, testing techniques, and simulation to (formally) test security properties in ICS networks

Sittin'On the Dock of the (WiFi) Bay: On the Frame Aggregation under IEEE 802.11 DCF

It is well known that frame aggregation in Internet communications improves transmission efficiency. However, it also causes a delay that for some real-time communications is inappropriate, thus creating a trade-off between efficiency and delay. In this paper, we establish the conditions for frame aggregation under the IEEE 802.11 DCF protocol to be beneficial on average delay. To do so, we first describe the transmission time in IEEE 802.11 in a stochastic framework and then we calculate the optimal value of the frames that, when aggregated, saves transmission time in the long term. Our findings, discussed with numerical experimentation, show that frame aggregation reduces transmission congestion and transmission delays